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<html xmlns="http://www.w3.org/1999/xhtml"><head><link rel="stylesheet" type="text/css" href="insn.css"/><meta name="generator" content="iform.xsl"/><title>DSB -- A64</title></head><body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">DSB</h2>
      <p class="aml">Data Synchronization Barrier is a memory barrier that ensures the completion of memory accesses, see <a class="armarm-xref" title="Reference to Armv8 ARM section">Data Synchronization Barrier</a>.</p>
      <p class="aml">A DSB instruction with the nXS qualifier is complete when the subset of these memory accesses with the XS attribute set to 0 are complete. It does not require that memory accesses with the XS attribute set to 1 are complete.</p>
    <p class="desc">This instruction is used by the aliases <a href="pssbb_dsb.html" title="Physical Speculative Store Bypass Barrier">PSSBB</a>, and <a href="ssbb_dsb.html" title="Speculative Store Bypass Barrier">SSBB</a>.</p>
    <p class="desc">
      It has encodings from 2 classes:
      <a href="#iclass_dsb_memory">Memory barrier</a>
       and 
      <a href="#iclass_dsb_nxs">Memory nXS barrier</a>
    </p>
    <h3 class="classheading"><a id="iclass_dsb_memory"/>Memory barrier</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="l">0</td><td class="r">0</td><td class="l">0</td><td>1</td><td class="r">1</td><td class="l">0</td><td>0</td><td>1</td><td class="r">1</td><td colspan="4" class="lr">CRm</td><td class="lr">1</td><td class="l">0</td><td class="r">0</td><td class="l">1</td><td>1</td><td>1</td><td>1</td><td class="r">1</td></tr><tr class="secondrow"><td colspan="10"/><td/><td colspan="2"/><td colspan="3"/><td colspan="4"/><td colspan="4"/><td/><td colspan="2" class="droppedname">opc</td><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="DSB_BO_barriers"/><p class="asm-code">DSB  <a href="#sa_option" title="Specifies the limitation on the barrier operation (field CRm)">&lt;option&gt;</a>|#<a href="#sa_imm" title="4-bit unsigned immediate [0-15] (field &quot;CRm&quot;)">&lt;imm&gt;</a></p></div><p class="pseudocode">boolean nXS = FALSE;

<a href="shared_pseudocode.html#DSBAlias" title="enumeration DSBAlias {DSBAlias_SSBB, DSBAlias_PSSBB, DSBAlias_DSB}">DSBAlias</a> alias;
case CRm of
    when '0000' alias = <a href="shared_pseudocode.html#DSBAlias_SSBB" title="enumeration DSBAlias {DSBAlias_SSBB, DSBAlias_PSSBB, DSBAlias_DSB}">DSBAlias_SSBB</a>;
    when '0100' alias = <a href="shared_pseudocode.html#DSBAlias_PSSBB" title="enumeration DSBAlias {DSBAlias_SSBB, DSBAlias_PSSBB, DSBAlias_DSB}">DSBAlias_PSSBB</a>;
    otherwise alias = <a href="shared_pseudocode.html#DSBAlias_DSB" title="enumeration DSBAlias {DSBAlias_SSBB, DSBAlias_PSSBB, DSBAlias_DSB}">DSBAlias_DSB</a>;

<a href="shared_pseudocode.html#MBReqDomain" title="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain</a> domain;
case CRm&lt;3:2&gt; of
    when '00' domain = <a href="shared_pseudocode.html#MBReqDomain_OuterShareable" title="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_OuterShareable</a>;
    when '01' domain = <a href="shared_pseudocode.html#MBReqDomain_Nonshareable" title="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_Nonshareable</a>;
    when '10' domain = <a href="shared_pseudocode.html#MBReqDomain_InnerShareable" title="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_InnerShareable</a>;
    when '11' domain = <a href="shared_pseudocode.html#MBReqDomain_FullSystem" title="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_FullSystem</a>;

<a href="shared_pseudocode.html#MBReqTypes" title="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes</a> types;
case CRm&lt;1:0&gt; of
    when '00' types = <a href="shared_pseudocode.html#MBReqTypes_All" title="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes_All</a>; domain = <a href="shared_pseudocode.html#MBReqDomain_FullSystem" title="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_FullSystem</a>;
    when '01' types = <a href="shared_pseudocode.html#MBReqTypes_Reads" title="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes_Reads</a>;
    when '10' types = <a href="shared_pseudocode.html#MBReqTypes_Writes" title="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes_Writes</a>;
    when '11' types = <a href="shared_pseudocode.html#MBReqTypes_All" title="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes_All</a>;</p>
    <h3 class="classheading"><a id="iclass_dsb_nxs"/>Memory nXS barrier<span style="font-size:smaller;"><br/>(FEAT_XS)
          </span></h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td class="r">1</td><td colspan="2" class="lr">imm2</td><td class="l">1</td><td class="r">0</td><td class="lr">0</td><td class="l">0</td><td class="r">1</td><td class="l">1</td><td>1</td><td>1</td><td>1</td><td class="r">1</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="DSB_BOn_barriers"/><p class="asm-code">DSB  <a href="#sa_option_1" title="Specifies the limitation on the barrier operation">&lt;option&gt;</a>nXS</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-shared.HaveFeatXS.0" title="function: boolean HaveFeatXS()">HaveFeatXS</a>() then UNDEFINED;
<a href="shared_pseudocode.html#MBReqTypes" title="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes</a> types = <a href="shared_pseudocode.html#MBReqTypes_All" title="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes_All</a>;
boolean nXS = TRUE;
<a href="shared_pseudocode.html#DSBAlias" title="enumeration DSBAlias {DSBAlias_SSBB, DSBAlias_PSSBB, DSBAlias_DSB}">DSBAlias</a> alias = <a href="shared_pseudocode.html#DSBAlias_DSB" title="enumeration DSBAlias {DSBAlias_SSBB, DSBAlias_PSSBB, DSBAlias_DSB}">DSBAlias_DSB</a>;
<a href="shared_pseudocode.html#MBReqDomain" title="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain</a> domain;

case imm2 of
    when '00' domain = <a href="shared_pseudocode.html#MBReqDomain_OuterShareable" title="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_OuterShareable</a>;
    when '01' domain = <a href="shared_pseudocode.html#MBReqDomain_Nonshareable" title="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_Nonshareable</a>;
    when '10' domain = <a href="shared_pseudocode.html#MBReqDomain_InnerShareable" title="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_InnerShareable</a>;
    when '11' domain = <a href="shared_pseudocode.html#MBReqDomain_FullSystem" title="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_FullSystem</a>;</p>
  <div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;option&gt;</td><td><a id="sa_option"/>
        
          
        
        
          <p class="aml">For the memory barrier variant: specifies the limitation on the barrier operation. Values are:</p>
          <dl>
            <dt>SY</dt><dd>Full system is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. This option is referred to as the full system barrier. Encoded as CRm = 0b1111.</dd>
            <dt>ST</dt><dd>Full system is the required shareability domain, writes are the required access type, both before and after the barrier instruction. Encoded as CRm = 0b1110.</dd>
            <dt>LD</dt><dd>Full system is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as CRm = 0b1101.</dd>
            <dt>ISH</dt><dd>Inner Shareable is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. Encoded as CRm = 0b1011.</dd>
            <dt>ISHST</dt><dd>Inner Shareable is the required shareability domain, writes are the required access type, both before and after the barrier instruction. Encoded as CRm = 0b1010.</dd>
            <dt>ISHLD</dt><dd>Inner Shareable is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as CRm = 0b1001.</dd>
            <dt>NSH</dt><dd>Non-shareable is the required shareability domain, reads and writes are the required access, both before and after the barrier instruction. Encoded as CRm = 0b0111.</dd>
            <dt>NSHST</dt><dd>Non-shareable is the required shareability domain, writes are the required access type, both before and after the barrier instruction. Encoded as CRm = 0b0110.</dd>
            <dt>NSHLD</dt><dd>Non-shareable is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as CRm = 0b0101.</dd>
            <dt>OSH</dt><dd>Outer Shareable is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. Encoded as CRm = 0b0011.</dd>
            <dt>OSHST</dt><dd>Outer Shareable is the required shareability domain, writes are the required access type, both before and after the barrier instruction. Encoded as CRm = 0b0010.</dd>
            <dt>OSHLD</dt><dd>Outer Shareable is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as CRm = 0b0001.</dd>
          </dl>
          <p class="aml">All other encodings of "CRm", other than the values 0b0000 and 0b0100, that are not listed above are reserved, and can be encoded using the #&lt;imm&gt; syntax. All unsupported and reserved options must execute as a full system barrier operation, but software must not rely on this behavior. For more information on whether an access is before or after a barrier instruction, see <a class="armarm-xref" title="Reference to Armv8 ARM section">Data Memory Barrier (DMB)</a> or see <a class="armarm-xref" title="Reference to Armv8 ARM section">Data Synchronization Barrier (DSB)</a>.</p>
          <div class="note"><hr class="note"/><h4>Note</h4>
            <p class="aml">The value 0b0000 is used to encode SSBB and the value 0b0100 is used to encode PSSBB.</p>
          <hr class="note"/></div>
        
      </td></tr><tr><td/><td><a id="sa_option_1"/>
        
          
        
        
          <p class="aml">For the memory nXS barrier variant: specifies the limitation on the barrier operation. Values are:</p>
          <dl>
            <dt>SY</dt><dd>Full system is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. This option is referred to as the full system barrier. Encoded as imm2 = 0b11.</dd>
            <dt>ISH</dt><dd>Inner Shareable is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. Encoded as imm2 = 0b10.</dd>
            <dt>NSH</dt><dd>Non-shareable is the required shareability domain, reads and writes are the required access, both before and after the barrier instruction. Encoded as imm2 = 0b01.</dd>
            <dt>OSH</dt><dd>Outer Shareable is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. Encoded as imm2 = 0b00.</dd>
          </dl>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;imm&gt;</td><td><a id="sa_imm"/>
        
          <p class="aml">Is a 4-bit unsigned immediate, in the range 0 to 15, encoded in the "CRm" field.</p>
        
      </td></tr></table></div><div class="syntax-notes"/><h3 class="aliastable" id="">Alias Conditions</h3><table class="aliastable"><thead><tr><th>Alias</th><th>Is preferred when</th></tr></thead><tbody><tr><td><a href="pssbb_dsb.html" title="Physical Speculative Store Bypass Barrier">PSSBB</a></td><td class="notfirst"><span class="pseudocode">CRm == '0100'</span></td></tr><tr><td><a href="ssbb_dsb.html" title="Speculative Store Bypass Barrier">SSBB</a></td><td class="notfirst"><span class="pseudocode">CRm == '0000'</span></td></tr></tbody></table>
    <div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3>
      <p class="pseudocode">case alias of
    when <a href="shared_pseudocode.html#DSBAlias_SSBB" title="enumeration DSBAlias {DSBAlias_SSBB, DSBAlias_PSSBB, DSBAlias_DSB}">DSBAlias_SSBB</a>
        <a href="shared_pseudocode.html#impl-shared.SpeculativeStoreBypassBarrierToVA.0" title="function: SpeculativeStoreBypassBarrierToVA()">SpeculativeStoreBypassBarrierToVA</a>();
    when <a href="shared_pseudocode.html#DSBAlias_PSSBB" title="enumeration DSBAlias {DSBAlias_SSBB, DSBAlias_PSSBB, DSBAlias_DSB}">DSBAlias_PSSBB</a>
        <a href="shared_pseudocode.html#impl-shared.SpeculativeStoreBypassBarrierToPA.0" title="function: SpeculativeStoreBypassBarrierToPA()">SpeculativeStoreBypassBarrierToPA</a>();
    when <a href="shared_pseudocode.html#DSBAlias_DSB" title="enumeration DSBAlias {DSBAlias_SSBB, DSBAlias_PSSBB, DSBAlias_DSB}">DSBAlias_DSB</a>
        if <a href="shared_pseudocode.html#impl-shared.HaveTME.0" title="function: boolean HaveTME()">HaveTME</a>() &amp;&amp; TSTATE.depth &gt; 0 then
            <a href="shared_pseudocode.html#impl-aarch64.FailTransaction.2" title="function: FailTransaction(TMFailure cause, boolean retry)">FailTransaction</a>(<a href="shared_pseudocode.html#TMFailure_ERR" title="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_ERR</a>, FALSE);
        if !nXS &amp;&amp; <a href="shared_pseudocode.html#impl-shared.HaveFeatXS.0" title="function: boolean HaveFeatXS()">HaveFeatXS</a>() then
            nXS = PSTATE.EL IN {<a href="shared_pseudocode.html#EL0" title="constant bits(2) EL0 = '00'">EL0</a>, <a href="shared_pseudocode.html#EL1" title="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a href="shared_pseudocode.html#impl-aarch64.IsHCRXEL2Enabled.0" title="function: boolean IsHCRXEL2Enabled()">IsHCRXEL2Enabled</a>() &amp;&amp; HCRX_EL2.FnXS == '1';
        <a href="shared_pseudocode.html#impl-shared.DataSynchronizationBarrier.3" title="function: DataSynchronizationBarrier(MBReqDomain domain, MBReqTypes types, boolean nXS)">DataSynchronizationBarrier</a>(domain, types, nXS);
    otherwise
        <a href="shared_pseudocode.html#impl-shared.Unreachable.0" title="function: Unreachable()">Unreachable</a>();</p>
    </div>
  <hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
      Internal version only: isa v33.62, AdvSIMD v29.12, pseudocode v2023-03_rel, sve v2023-03_rc3b
      ; Build timestamp: 2023-03-31T11:36
    </p><p class="copyconf">
      Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved.
      This document is Non-Confidential.
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